Design Principles and Selection Considerations for Fractional Frequencies in Crystal Oscillators
In the design of hardware clock systems, engineers often encounter a class of seemingly "irregular" crystal oscillator frequencies, such as 11.0592 MHz, 3.579545 MHz, and 19.6608 MHz. These frequencies with decimal components are not chosen arbitrarily, but are the inevitable result of design considerations based on communication protocols, frequency-division constraints, and system-level reverse requirements. Starting from the fundamental principles, this article analyzes the logic behind the generation of fractional frequencies and provides practical screening methods for component selection.
- Core Design Logic of Fractional Frequency Points
As the system clock source, the crystal oscillator's frequency selection is always tailored to meet the precise timing requirements of downstream digital circuits (such as PLLs, dividers, and serial communication). The emergence of fractional frequency points primarily stems from the following four types of design constraints:
1.Adapting to UART Integer Division to Ensure Error-Free Serial Baud Rates
The serial baud rate is derived from the system clock through integer division, according to the following formula: Baud rate = Clock frequency / Division factor
To accurately generate standard baud rates (such as 9600, 19200, or 115200 bps), the clock frequency must be divisible by the divisor without a remainder. Taking 1.8432 MHz as an example, after 16-fold oversampling division:
1.8432 MHz ÷ 16 = 115.2 kHz, which equals 115200 bps.
Similarly, 11.0592 MHz and 19.6608 MHz are 6 times and 10.666… times 1.8432 MHz, respectively (actually, 11.0592 = 1.8432 × 6, 19.6608 = 1.8432 × 10.666… requires a PLL), but it is more common to use them directly as the clock frequency for MCUs such as the 51 micro-controller, allowing the internal UART divider to generate all standard baud rates through division. If an integer frequency of 20 MHz is selected, it cannot be evenly divided by 115,200, resulting in cumulative error and causing frame errors or packet loss.
2.Support for a binary frequency-division architecture simplifies clock tree design
Frequencies such as 20.48 MHz, 10.24 MHz, and 5.12 MHz can all be expressed as 2ⁿ × 10 kHz (e.g., 20.48 MHz = 2048 × 10 kHz). After cascading these frequencies through binary frequency division, sub-clock domains such as 10.24 MHz, 5.12 MHz, 2.56 MHz, 1.28 MHz, and so on can be generated. This approach is well-suited for implementing frequency division using binary counters or shift registers, resulting in a simple circuit structure with well-defined phase relationships and consistent timing margins between the various frequency-divided clocks. These frequencies are commonly used as base frequencies in industrial DSPs, PLCs, and servo drives.
3.Synthesized via PLL to meet high-speed communication and audio/video sampling standards
Modern SoCs, optical modules, and video processors incorporate PLLs, which typically use standard integer frequencies (such as 25 MHz or 24 MHz) as a reference and then generate specific non-standard frequencies through integer division or multiplication, or fractional division. Typical examples include:
74.25 MHz: The high-definition video sampling clock defined by the SMPTE standard, used for formats such as 1080i and 720p;
33.1776 MHz: Commonly found in audio codecs and broadband RF front-ends; when used with a PLL, it can precisely generate the 44.1 kHz or 48 kHz audio sampling rate families;
25.000625 MHz: Certain Ethernet PHYs use a 25 MHz clock with a fractional PLL to generate a precise 125 MHz serial data rate to support a 1 Gbps line rate (note that integer multiples of 25 MHz are commonly used in practice; this is provided here for illustrative purposes only).
It should be noted that fractional frequency division introduces deterministic jitter and spurious signals. For applications sensitive to phase noise, priority should be given to target frequencies that can be obtained directly through integer frequency division, or to the use of low-noise PLLs with appropriately configured loop bandwidths.
4.Adherence to Historical Industry Protocols and EMC Considerations
Historical Protocols: USB 2.0 specifies a 48 MHz high-speed clock; Ethernet MACs use 25 MHz or 125 MHz; and real-time clocks (RTCs) operate at 32.768 kHz (2¹⁵ Hz). These frequencies were fixed when the standards were established and have since been adopted across the entire industry chain, becoming de facto standards.
Electromagnetic Compatibility (EMC): Higher-order harmonics of integer frequencies may overlap with power supply, RF, or wireless communication bands, introducing interference. Selecting an oscillator frequency with a fractional component can disperse or shift harmonic energy, thereby reducing EMI risks and lowering the costs of filtering and shielding.
- Other Key Factors in Crystal Oscillator Selection
In addition to the frequency value, the following engineering factors are equally important for selection:
Phase Noise and Jitter
Although PLLs can synthesize any frequency, fractional frequency division significantly degrades near-end phase noise and random jitter. For applications such as high-speed optical modules, millimeter-wave radar, or 5G fronthaul, it is recommended to directly select crystal oscillators with native frequencies that meet phase noise specifications to avoid insufficient signal integrity margins later on.
Lead Time and Cost
Non-standard or custom frequencies typically require long lead times and incur high engineering costs. Within acceptable performance limits, priority should be given to industry-standard frequencies (such as common integer frequencies like 25 MHz, 27 MHz, 40 MHz, and 50 MHz, as well as the standard fractional frequencies mentioned in this article) to shorten the R&D cycle and control BOM costs.
Compatibility with Domestic Substitutes
Currently, domestic quartz crystal oscillator manufacturers cover the vast majority of commonly used integer and fractional standard frequencies. When selecting a device, focus on supply stability, temperature characteristics (such as ±10 ppm and ±20 ppm), and load capacitance parameters to ensure compatibility with the clock input requirements of the host controller chip.
- Practical Selection Recommendations
First, determine the system clock constraints: List the precise clock frequencies required by all peripherals (UART, I2S, SPI, Ethernet, USB, Video) and their permissible error margins.
Derive the crystal oscillator fundamental frequency in reverse: If the microcontroller has a built-in PLL, select a reference crystal oscillator capable of generating the target frequencies through integer or low-fractional division ratios. Give priority to frequencies with a division ratio less than 100 and a denominator that is a power of 2.
Verify the division error: Calculate whether the division error is less than the maximum baud rate/sampling rate deviation allowed by the peripherals (typically < ±2%).
Assess EMI risk: Perform a spectral analysis of high-frequency harmonics; if necessary, select a frequency point that deviates from integer-order harmonics.
Consider availability and cost: While meeting performance requirements, select a model with ample market availability and a package type (e.g., HC-49S, SMD 3.2 × 2.5 mm) that meets production requirements.